[Introduction]In the first to fifth parts of this series of articles[1-5]In this paper, we extensively introduce the development of 25 kW electric vehicle charging piles from a hardware perspective and control strategy. Figure 1 represents the system discussed so far.
In Part VI, we turn our attention to the gate drive circuits required to drive SiC MOSFETs. Because these transistors are more efficient and reliable, they are rapidly gaining popularity in the power semiconductor market. With more and more devices on the market, designers must understand the commonalities and differences between SiC MOSFETs and silicon (Si) IGBTs and silicon superjunction (SJ) MOSFETs so that users can take full advantage of each device.
This article is based on the experience gained in building a 25 kW fast electric vehicle charging station using Onsemi’s new SiC modules. These modules use ON Semiconductor’s M1 1200-V SiC MOSFETs. We will learn how to design and tune the combination of coupled gate drivers and SiC MOSFETs in high power applications.
In this design, we will use ON Semiconductor’s IGBT galvanically isolated gate driver as a starting point and describe improvements made using the new dedicated SiC galvanically isolated gate driver. All gate driver families described in this article use the same isolation technology and output stage technology.
Figure 1. High-level block diagram of a 25 kW electric vehicle DC charging pile
Gate Drive Requirements: SiC MOSFETs, Silicon IGBTs and SJ MOSFETs
For IGBTs and MOSFETs (silicon and silicon carbide), the gate must be charged to turn on the device, and the gate must be discharged to turn off the device. For both cases, the current is somewhat common, as shown in Figure 2.
Figure 2. The current paths when the gate drive circuit is turned on (a) and turned off (b) are shown as green and red arrows, respectively
However, the gate voltage ranges of the three devices (IGBT, silicon SJ MOSFET and SiC MOSFET) are different. For IGBTs, the turn-on voltage is around 15 V and the turn-off voltage is typically around -8 V. For SJ MOSFETs, the turn-on voltage is about 10 V and the turn-off voltage is typically 0 V. For SiC MOSFETs, as the gate voltage increases, RDS(ON) decreases, so the maximum gate voltage can be applied for maximum efficiency. Therefore, the gate-on voltage can vary from 15 V to 20 V, depending on technology or product generation.
At turn-on voltages below 15 V, the slope of the SiC MOSFET curve is negative, making paralleling devices difficult. The shutdown voltage can be reduced from 0 V to -5 V. ON Semiconductor SiC MOSFETs can be blocked with 0 V, -3 V, or -5 V, depending on the trade-off between efficiency and complexity of the gate driver circuit, and sometimes depending on which generation of SiC MOSFETs are used. The range of gate voltage (or turn-on voltage) directly affects the undervoltage lockout (UVLO) required by the gate driver.
As a first approach, the IGBT gate driver output voltage range is more similar to the needs of SiC MOSFETs than SJ MOSFETs. First, it is highly recommended to use negatively biased gate drives with SiC MOSFETs (such as IGBTs) in switching applications to reduce the effects of parasitic inductance introduced by non-ideal PCB layout during high di/dt and dV/dt switching Ringing of power transistor gate-source drive voltage.
Additionally, since the threshold voltage of our SiC MOSFETs is around 1.5 V, negative voltage blocking provides greater tolerance for noise (caused by dV/dt and di/dt) to generate unwanted turn-on in the off-state .
Second, negative voltage blocking results in lower leakage current in the off-state. Therefore, static losses will be lower. Finally, negative voltage blocking has faster or shorter turn-on and turn-off times than zero voltage blocking.
To achieve fast turn-on and turn-off, or to maintain output regulation during drain/collector voltage transients, the output driver stage requires very low output impedance. The maximum value of drive current depends on the power rating of the application and is similar for all types of devices.
The maximum current required to charge the gate depends on
● Desired amount of gate charge
● Topology (hard or soft switching, ie ZVS)
● Maximum dV/dt required to limit EMI with (external plus internal) gate resistors
Even if the (external plus internal) gate resistors limit the amount of current in the application, the current the driver can source and sink should be higher than the required maximum current. This will help provide a safety margin to maintain the required maximum current at the maximum operating temperature and prevent the driver from reducing current capability due to self-heating.
Since SiC MOSFETs have significantly higher turn-on and turn-off speeds compared to IGBTs or SJ MOSFETs, SiC devices can operate at much higher switching frequencies than silicon devices. Therefore, in a half-bridge configuration, the rate of change of the switch node voltage is very fast. A dV/dt of up to 100 V/ns can be achieved using SiC MOSFETs. The driver should be able to source and sink the desired current induced by the dV/dt applied to the gate by the Miller capacitor (or capacitance between drain/collector and gate). During this dV/dt transient, the gate driver output signal should always be set at the value given by the input signal.
To supplement the sink current sink capability or enhance the Miller effect current sink, gate clamps can be used. This clamp will reinforce the blocking voltage with very low impedance and bypass the blocking or turn-off gate resistor. The clamping time is from after turn-off until the early onset of turn-on. This technology is suitable for very high power requirements to drive large Miller capacitor devices. Our 25 kW electric vehicle charging station application is one such example.
Furthermore, in the case of isolated or floating drivers, the common-mode transient immunity (CMTI) between the driver input stage and output stage of the SiC device driver should be stronger than that of the silicon device driver. The applied gate drive voltage should remain stable.
In summary, for all types of switches, there should be no glitches at the driver output during the switching node, drain/collector, or dV/dt between the driver input and output stages. However, since SiC MOSFETs are faster, SiC MOSFET drivers will be more stringent in terms of these requirements (higher CMTI and dV/dt immunity, higher current ratings, and lower output impedance).
Timing is an important concern due to the fast switching speed of our half-bridge architecture. When the device operates in a half bridge, there are two timing parameters to consider: the propagation delay from input to output and the delay mismatch between the two drivers or between the two outputs.
For SiC, the propagation delay affects the duty cycle accuracy since the switching frequency is likely to be higher than 100 kHz. Mismatch affects the dead time between switches. For SiC drivers, a propagation delay of less than 50 ns and a delay mismatch of less than 10 ns are suitable.
For high-speed applications, SiC MOSFETs can be driven using silicon or SJ MOSFET gate drivers, which are generally faster than IGBT drivers. However, these drivers may not provide the desired output voltage range. The turn-on voltage (or output voltage swing) of these drivers is typically limited to 15 V. This is too low for a SiC MOSFET. Also, most silicon MOSFET drivers do not support negative voltage blocking.
Specific Requirements for 25 kW Applications
Rise/Fall Time and Source/Sink Current Requirements
Due to the need to control EMI, we will limit the dV/dt, but not too much, so as to shorten the dead time (or speed up the on/off time) and achieve high efficiency. Such as AND90103/DThe gate resistance ranges from 2 to 5 Ω, and the dV/dt range of SiC MOSFETs can reach 20 to 40 V/ns. Therefore, this range has been taken into account when selecting the gate resistance. The choice of gate resistor value was adjusted and verified using SPICE simulations by evaluating dV/dt during the on/off time.
During hardware development, we follow the IEC-61851 standard, which requires compliance with the rules of IEC-60664-1. We assume that the operating voltage is close to the maximum value of 1000 V. NCD57000 A gate driver is a good choice. The driver has a dielectric strength isolation voltage of over 5 kVrms, an operating voltage VIORM capability of over 1200 V, and is UL 1577 compliant. Wide body 8mm creepage helps meet creepage/clearance requirements.
Features and Protection
The following gate driver features improve the robustness of SiC MOSFET power implementations, increasing the efficiency and reliability of the application. These key features include:
● Common mode transient immunity is a key parameter for SiC applications. NCD57000 provides 100 kV/µs immunity
● Active Miller clamp
● DESAT protection
● Soft shutdown under DESAT
The NCD57000 IGBT driver integrates all these features. It also includes negative drive or negative turn-off voltage.
Gate Driver Power Supply for SiC MOSFETs
Using SECO-LVDCDC3064-SIC-GEVBThe isolated power supply serves as the power supply for the SiC drive circuit, providing the required -5 V and 20 V regulated voltage rails to drive SiC transistors efficiently. The transformer safety specification complies with IEC 62368-1 and IEC 61558-2-16 standards and has a dielectric insulation characteristic of 4 kVac.
Implementation of SiC gate driver
DESAT protection calculation
According to AND9949/DCalculate the desaturation current of a SiC transistor. Use a 14.3 kΩ resistor to set the DESAT current to trigger in the 85 to 115 A range (Figure 3). The DESAT current is evaluated and fine-tuned during the prototype stage.
The following factors have been considered:
VTH = 9.0 V, RDS(ON) = 11 mΩ at 100 A, US1MFA, VF = 309.5 mV at 500 μA (simulation).
A 22 pF capacitor placed on the DESAT pin adds 430 ns to the blanking time for a total blanking time of 880 ns. The internal filter time given in the data sheet is 320 ns, so the total reaction time to desaturation events is equal to 1.2 μs. Adding the time required to turn off the SiC transistor, the total time required for DESAT action is less than 2.0 μs.
Figure 3. Gate driver NCD57000 connected with DESAT function element (calculated value)
Verification of SiC MOSFET Switches by Simulation
PFC and DC-DC power stage simulation models include a gate driver model to evaluate switching performance with gate-source resistances RG1 = 1.8 Ω and RG2 = 100 kΩ (see Figure 4 for the definition or location of RG1 and RG2) .
In this example, only RG1 contributes to the discharge of the gate capacitance of the SiC MOSFET. The PFC model contains three half-bridge SiC modules as well as gate drivers. But only one half-bridge connection is shown in Figure 4. See the third part of this series for the SPICE model of the SiC module.
Figure 4. Power stage and gate driver model for PFC phase A
The driver stage has a significant impact on system performance (especially for SiC-based systems). Therefore, it is strongly recommended to incorporate it into simulation – at least to some extent.
One of the challenges is that the existing gate driver models are often so complex that they slow down the simulation and increase the simulation runtime because they include all the features of the driver (such as UVLO, clamping, and DESAT, etc.). In general, for power stage simulation, and more specifically for the goals of this project, a simplified model of the gate driver is sufficient. The models we build only include propagation delay and output stage characteristics or performance.
Although detailed IV characteristics are usually not provided directly in the various driver data sheets, for some given points, use the rated driver output capability (sink current IPK-SNK1 and output current IPK-SRC1 peak current, see NCD57001 Data Sheet), combined with the propagation delay information, an approximation of the output characteristics can be obtained. This approximation method improves simulation accuracy while still providing acceptable simulation times. Figure 5 shows a SPICE model of the NCD57001 gate driver created based on the values in the data sheet.
Figure 5. NCD57001 SPICE simplified model based on data sheet values
Simulation of off transitions: turn-on and turn-off
One of the key parameters for evaluating the switching performance of a PFC stage is the switching transition speed (see Figure 6), in other words, the dV/dt of the MOSFET. Theoretically, the faster the switching speed, the lower the switching losses exhibited and the higher the efficiency.
However, the switching speed is also limited by other factors. For example, the transistor’s own tolerance to such high gradients and EMI or other common-mode (CM) noise created by fast switching.
The layout itself and parasitic inductance and capacitance also add constraints.
Figure 6. Turn-on waveform of a PFC stage MOSFET
Figure 7 In the configuration presented in this simulation, the dV/dt value exceeds 66 V/ns, a high-speed switch that is only possible with wide-bandgap technology. In practice, such a high dV/dt still carries a high risk (even for SiC modules) that ultra-high overvoltage spikes from parasitic inductances can easily exceed the device’s upper withstand voltage limit.
Figure 7. Low-Side Phase A SiC MOSFET Turn-On Speed as a Function of Input Voltage as a Function of Inductor and Output Capacitor Values
Adjusting the gate resistance is the easiest way to reduce dV/dt. A larger gate resistor value reduces switching speed and reduces overall design risk, but also brings the disadvantage of a small power loss (since the switching speed is not as fast).
Based on the conclusion of this simulation, we decided to make a compromise solution and replace the gate resistor with a larger value (1.8 Ω—>4.7 Ω) to ensure that the dV/dt of the MOS transistor is 25 V/ns when it is turned on. about. This will be used as the initial value when verifying the actual hardware board.
Turn-off transitions are handled in a similar manner. Figures 8 and 9 show the results of these simulations. The turn-off transition is also fast (up to 40 V/ns) with a 1.8 Ω gate sink resistor (the same value used in the turn-on simulation). In the prototype design, the current sink resistor value was increased to 3.3 Ω to adjust the turn-off transition to around 25 V/ns.
Figure 8. Low-Side Phase A SiC MOSFET Turn-Off Speed as a Function of Input Voltage as a Function of Inductor and Output Capacitor Values
Figure 9. Typical turn-off waveform of a PFC stage MOSFET
PCB Layout and Recommendations
To eliminate or minimize PCB parasitics, SiC driver circuit layout is critical in SiC power supply design. Some suggestions and examples of good layout arrangements are shown in Figures 10 and 11. The output current, sink current, and clamp traces (see Figure 10) should be kept as short as possible. Close the source/sink current path with the VDD and VEE decoupling capacitors (shown in Figure 10). They must be placed as close as possible to the VDD and VEE gate driver pins, as shown in Figure 11.
Capacitor values should be large enough to feed sink and source current peaks while maintaining VDD and VEE levels. These decoupling capacitors should also have very little parasitics and be high frequency capacitors.
Figure 10. SiC gate drive circuit PCB layout.Arrows show source, sink, and clamp current paths in green, red, and light blue, respectively
Figure 11. Recommended placement of VEE and VDD decoupling capacitors
Future Enhancements for SiC Gate Drives
The NCD570xx IGBT gate driver family discussed above is sufficient to meet the requirements of SiC MOSFET gate drivers in high power applications. However, with an advanced version of the galvanic isolation transformer, faster transit times and smaller delay mismatches can be obtained.
Incorporating this improvement, the new NCP5156xA family of gate drivers is also available for driving SiC MOSFETs. The gate voltage range has been adjusted to match the gate on/off voltage of each generation of SiC MOSFETs; and the UVLO has been adjusted for the value of the gate voltage range.
Key features of the NCP5156x family include a propagation delay of 36 ns (typ). Maximum delay matching time of 8 ns per channel; output supply voltage range from 6.5 V to 30 V, supports 5 V, 8 V, and 17 V UVLO threshold voltages, CMTI >200 V/ns; input to each output Galvanic isolation is 5 kVrms (UL 1577 rated), peak differential voltage between output channels is 1200 V; user programmable dead time and 4.5 A/9 A peak source and sink current (Figure 12).
Figure 12. NCP51561 block diagram
When the output stage provides only a single supply (or unipolar) rail, the following schematic utilizes Zener diodes to obtain positive and negative supply (or bipolar) voltages (see Figure 13).
Figure 13. Negative Bias Using Zener Diodes on Single-Ended Isolated Bias Supply
Figure 14 shows the experimental results of using a Zener diode to achieve negative bias on the single-ended isolated power supply of the NCP51561 for SiC MOSFET gate drive applications. This example design is designed to provide +15 V and -5.1 V drive capability with the device source as the reference using an isolated 20 V supply.
Figure 14. Experimental waveforms for negative bias using a Zener diode on a single-ended isolated power supply (where CH1: Input[2 V/div]CH2: output[5 V/div])
Since the NCP5156x ICs are integrated Miller clamps, they are more recommended for low power SiC MOSFET applications. For powers above tens of kilowatts, the Miller clamp shown in this article is recommended. To this end, we will introduce new devices NCD57100 and NCD57101 (pin compatible with NCD57000 and NCD57001 respectively) with extended gate voltage range.
This new extended gate voltage range is more suitable for driving SiC MOSFETs. In the new device NCD571xx, this range is up to 36 V, compared to 25 V for the NCD570xx used in this 25 kW electric vehicle charging station application.
This article details the factors that must be considered when designing and tuning gate drivers for SiC MOSFETs in 25 kW power applications. This article starts with the existing NCD57001 IGBT galvanically isolated gate driver, goes on to explain the improvements made in a dedicated SiC galvanically isolated gate driver, and introduces the new device families NCP5156x and NCD571xx for driving SiC MOSFETs.
SiC MOSFETs are much faster than existing silicon MOSFETs and IGBTs. Therefore, SiC MOSFET drivers require higher common-mode transient immunity and dV/dt immunity, higher current ratings, and lower output impedance. Using the devices, tips and tricks mentioned in this article, designers can achieve the performance of SiC MOSFET drivers required by their applications.
This series of articles consists of eight parts, and we will publish the seventh and eighth parts in succession.
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