“The current demand for bandwidth is exploding, pushing carrier frequencies into the tens of gigahertz. At these high frequencies, customers can use higher bandwidths without worrying about overcrowding the spectrum. However, as frequencies increase, instrumentation solutions for these devices and frequencies become extremely complex. This is because the instrumentation solution needs to improve performance by an order of magnitude to avoid damaging the device under test.
The current demand for bandwidth is exploding, pushing carrier frequencies into the tens of gigahertz. At these high frequencies, customers can use higher bandwidths without worrying about overcrowding the spectrum. However, as frequencies increase, instrumentation solutions for these devices and frequencies become extremely complex. This is because the instrumentation solution needs to improve performance by an order of magnitude to avoid damaging the device under test. This article will introduce several low phase noise signal generation methods. We will demonstrate the advantages and disadvantages of these methods and introduce conversion loop devices that take advantage of all frequency generation methods without adding complexity to generate ultra-low phase noise signals.
Phase-locked loop circuit analysis
Phase Locked Loop (PLL) circuits are common in many frequency generating devices. These devices ensure that the waveform generated within the device and the reference signal are phase aligned or locked to the reference signal. Figure 1 is a simplified block diagram of a PLL. The output of the voltage-controlled oscillator (VCO) is divided by an N counter and compared with a reference signal in a phase frequency detector (PFD) circuit. This simple circuit has been the subject of many textbooks and has been extensively studied. We’ll use some well-known basics to determine how to drastically reduce phase noise at the output.
Figure 1. Phase-locked loop circuit.
The overall phase noise of a PLL circuit arises from the inherent imperfections or phase noise of each building block. The phase noise of each associated block can be modeled and the overall phase noise of the PLL can be accurately predicted through simulation and analytical calculations. Let’s review each block below and discuss their impact on output phase noise.
The PFD module compares the reference signal to the divided output frequency. The error signal generated by this module is fed into a charge pump circuit, which generates a control voltage that controls the VCO until the output phase of the device matches the reference phase. Most modern frequency generation devices with integrated PFD circuits provide a figure of merit (FOM) in the data sheet. The in-band phase noise can be calculated using the FOM as follows:
where fPFDis the PFD frequency and N is the value of the output frequency divider. Note that the output frequency is fPFDand the product of the N divider value. For a given output frequency, fPFDIncrease by a factor and the value of N decreases by the same factor. due to fPFD, reducing the value of N will reduce the phase noise by a factor of two, thus reducing the overall output phase noise. We can conclude that the higher the PFD frequency, the lower the near-end phase noise of the carrier. This finding will be used in the remainder of this article.
The loop filter tracks the PFD and smoothes the error signal generated by the PFD device. Its design uses several system parameters, such as charge pump current, VCO sensitivity, and PFD frequency. A less important function of the loop filter is to determine the bandwidth of the negative feedback control loop. The reference signal affects the phase noise of the output signal within the control bandwidth of the loop filter. Beyond this cutoff frequency, the overall phase noise performance will be dominated by the characteristics of the VCO. We will use this in the next sections to optimize the overall phase noise of the system.
The VCO produces an output frequency based on a control voltage applied to its input. The output frequency of the VCO is updated by the control loop until the phase locks with that of the reference signal. The VCO directly affects the overall phase noise of the system. Generally speaking, as the quality of the VCO increases, the phase noise decreases. However, increasing the quality often limits the overall tunable range of the device. VCOs for narrowband operation generally have very good phase noise performance.
Frequency generation options
Using oscillators of various quality levels and different topologies, the signal can be generated in a number of ways. Instrumentation applications typically strive for optimum performance in terms of low phase noise and spurious levels. Let’s review some frequency generation options that can achieve very low phase noise.
Use a fixed frequency oscillator to generate frequency
One type of signal generation device with excellent phase noise performance is the fixed frequency oscillator. These devices typically have a high figure of merit, resulting in excellent carrier near-end phase noise performance. These oscillators operate at a predetermined frequency, which is largely determined by the geometry and structure of the device, and have some tunability to allow their phase to lock to a reference source. Such devices include oven-controlled crystal oscillators (OCXOs), temperature-compensated crystal oscillators (TCXOs), and voltage-controlled SAW oscillators (VCSOs). A major disadvantage of fixed frequency oscillators is the limited frequency coverage of these devices. Most instrumentation devices require variable frequency coverage, although they may be suitable for devices operating at a fixed frequency or multiples thereof.
Figure 2. Using a fixed source to generate variable frequency.
One solution to this problem requires the use of direct digital synthesizers (DDS) or digital-to-analog converter (DAC) devices. A fixed frequency signal can be used to drive the sampling clock of the DDS device, as shown in Figure 2. The frequency of the oscillator can be multiplied as needed by a frequency multiplier or step recovery diode (SRD) and filtered before being applied to the DDS. DDS can generate any frequency in the first Nyquist zone, up to half the sampling frequency. Some modern DAC devices even work well in the second Nyquist zone. Figure 3 shows the output spectrum and phase noise plot of the AD9164 driven by a low phase noise dielectric resonant oscillator (DRO) at 6 GHz. The phase noise plot shows that the output phase noise is very low and the spurious level of the output spectrum is less than C70 dBc.
The spectral purity of the multiplied sampling clock directly affects the output of the device. Once the signal is multiplied, many harmonics appear at the output. The desired signal needs to be filtered to achieve low spurious levels at the DDS output. Typically, spurs that appear at the sample clock will appear at the output at similar levels. If the multiplier factor is large, the filter may need to be very sensitive, which requires a significantly steeper region.
In addition, the phase noise of the frequency multiplied signal increases as the frequency multiplication factor increases. For example, for every doubling of the signal frequency, the phase noise increases by 6 dB. Depending on the starting phase noise curve and the multiplication factor, the noise floor (far-end phase noise) can increase significantly, making the overall solution unattractive. This is a well-known dilemma, and the use of single-frequency, high-Q components with near-carrier phase noise introduces a far-carrier phase noise floor. For example, surface acoustic wave (SAW) devices have excellent carrier near-end phase noise performance at carrier frequencies around 1 GHz. Millimeter-wave devices operating above 40 GHz require a frequency multiplication factor of up to 40. This can increase the phase noise floor by 32 dB or more, making the solution less attractive.
Figure 3. Output spectrum and phase noise of the AD9164 at 800 MHz, using a fixed frequency oscillator as the sampling clock.
Frequency Generation Using Wideband PLL Devices
Wideband frequency synthesizers address many of the challenges associated with single-frequency devices. These devices, such as the ADF4372 microwave frequency synthesizer, use multiple VCO cores, each of which is further divided into overlapping frequency bands. This architecture enables a high quality factor for each core and band. Significantly improves overall device performance compared to architectures using a single core.
A key advantage of these devices is that the fundamental operating frequency is higher than that of crystal oscillators or SAW oscillators. Many modern VCOs have fundamental frequencies from 4 GHz to 20 GHz or even higher. This makes its carrier far-end phase noise performance more attractive in mmWave applications. For example, a device operating at a 10 GHz base frequency requires a multiplier of 4 to extend the frequency to 40 GHz. This means a 12 dB increase in the phase noise floor compared to 32 dB with a crystal oscillator.
One challenge associated with these multicore and multiband devices is finding the optimal band for synthesizing the target frequency. This may require creating a lookup table to identify the correct frequency band. Devices with automatic calibration, such as the ADF4372 and ADF5610, make this process easier and more reliable through temperature and process variations. This greatly simplifies the overall operation of the device, allows frequency changes to be simply programmed into the device’s registers, and automatically determines the optimal operating frequency band.
Another challenge is that the near-end phase noise of the carrier associated with these devices is typically much higher than with single-frequency devices. Even with a lower overall phase noise floor, higher carrier near-end phase noise translates into higher overall integrated noise. This may limit the use of these devices in applications requiring lower integrated phase noise.
The conversion loop method takes full advantage of all the frequency generation methods mentioned earlier, and eliminates their shortcomings. Let’s first summarize our findings so far before discussing the details of the conversion loop.
Single-frequency devices such as OCXO and SAW and crystal oscillators with high quality factor have good carrier near-end phase noise. These single-frequency devices typically have a lower fundamental frequency, so when multiplied to mmWave frequencies, the far-end phase noise performance of the carrier is slightly inferior. An ideal solution would have the near-end performance of these devices without adding phase noise to the far-end of the carrier.
A DDS or DAC device can generate a variable frequency from a fixed frequency device. These devices also suffer from the large multipliers required at mmWave frequencies and the need for filtering to suppress subharmonics and other interfering spurs. Tolerating these shortcomings leads to an ideal solution.
The wideband frequency synthesizer has a high fundamental frequency and excellent carrier far-end phase noise performance. However, these devices are not really high quality factors, so the near-end phase noise of the carrier is relatively poor compared to single-frequency devices. There is a need to take advantage of the far-end phase noise of the carrier without degrading the near-end phase noise performance of the carrier.
This brings us to the conversion loop device, shown in Figure 4. Instead of dividing the output frequency by a large divider value, a mixer is used to convert the output signal to an intermediate frequency (IF) that matches the frequency of the reference signal. This effectively reduces the divider value to 1, eliminating the noise that occurs when large divider values are used in traditional PLL devices. This causes the phase noise distribution of the LO to appear on the control loop. We can generate this LO signal using a single frequency device and DDS with excellent carrier near-end performance.
Figure 4. Conversion loop architecture.
Loop filter bandwidth is a key design parameter for switching loop devices. As mentioned earlier, the loop filter determines the overall bandwidth of the control loop. In other words, it defines how much the reference signal and the LO signal contribute to the output phase noise. In the conversion loop, we can choose a large loop filter bandwidth due to the extremely low near-end phase noise of the carrier. Figure 5 shows the phase noise curve of the conversion loop device and its LO input. Note that while the LO has a low near-carrier phase noise, the far-side noise floor of the carrier is high. The RF output tracks the LO phase noise up to the loop filter bandwidth. After this frequency offset, the far-end phase noise of the carrier is defined by the VCO, which is very low.
The conversion loop device essentially exploits the ideal carrier near-end performance of a single-frequency device using a DDS device as the LO, and takes advantage of the carrier far-end phase noise of a wideband VCO by choosing a large loop bandwidth. This not only solves the problem of which phase noise region to optimize, but also achieves extremely low output phase noise.
Figure 5. Phase noise curve of a conversion loop device.
The excellent phase noise performance of the conversion loop makes it useful in many mmWave instrumentation applications. In addition to phase noise performance, instrumentation solutions also need to suppress spurious signals to extremely low levels. This is very challenging for switching loop devices due to the presence of multiple strong signals at different frequencies. Preventing feedthrough of the LO and IF signals to the output is challenging in many cases. In addition, many intermodulation products of the IF, LO, and RF signals may be generated at the output. These spurious signals result in poor spurious performance of the entire instrumentation solution.
The ADF4401A, a fully integrated conversion loop device from Analog Devices, addresses many of these challenges. It eliminates all feedthrough paths that might exist in discrete solutions. This is achieved through the overall design of built-in shielding and minimized feedthrough mechanisms. In addition, it features spurious rejection of C90 dBc or lower, rivaling yttrium iron garnet (YIG) spherical oscillator solutions. Even if the input to the system is less than ideal, the output of the device has very low spurious levels. Figure 6a shows the output spectrum of the ADF4401A, where the LO input contains many spurs at a level of about C40 dBc, as shown in Figure 6b. Such LO signals are typically not available in instrumentation solutions due to the extensive filtering required. However, the ADF4401A accepts this LO input and produces the output spectrum shown in Figure 6a without any additional filtering.
Figure 6. (a) Conversion loop output spectrum at 6.5 GHz and (b) LO input spectrum at 3 GHz. Using the ADF4401A’s internal LO frequency multiplier, the effective LO frequency becomes 6 GHz. In this example, the IF frequency is 500 MHz.
The device features an automatic calibration engine that identifies the optimal VCO band for a given target frequency. In calibration mode, the device searches for the correct frequency band under actual temperature and process conditions, enabling a seamless frequency tuning process.
Instrumentation solutions require low carrier signal phase noise and low spurious signal levels to meet the needs of mmWave devices. While there are various ways to synthesize these signals, all have trade-offs, so the overall solution becomes increasingly complex. The ADF4401A ADI conversion loop device takes advantage of many different frequency generation schemes and removes their disadvantages. Excellent phase noise and excellent spurious performance are achieved without complex filtering.