“Designers need accurate and reliable oscillators that provide stable timing over a wide range of applications and operating temperatures. Discrete crystal-controlled oscillators can meet the required performance characteristics, but it is technically difficult to design with crystals effectively, and is time-consuming and unnecessary cost. In addition, it is not optimal in terms of external dimensions.
Author: Jeff Shepard
Circuit timing is a critical function required in many Electronic devices, including microcontrollers, USB, Ethernet, Wi-Fi and Bluetooth interfaces, as well as computing equipment and peripherals, medical equipment, test and measurement equipment, industrial control and automation, physical Internet of Things (IoT), wearables and consumer electronics. Designing a crystal-controlled oscillator to provide system timing may seem simple at first, but the designer must consider many parameters and design requirements when matching a quartz crystal to an oscillator IC.
There are many factors to consider, including crystal motion impedance, resonant modes, excitation power, and oscillator negative resistance. In terms of circuit layout, designers need to consider the parasitic capacitance of the PC board, add guard bands around the crystal, and integrate capacitors on-chip. The final design needs to be compact and reliable, with minimal component count, low root mean square (rms) jitter, and minimal power dissipation over a wide input voltage range.
Simple Packaged Crystal Oscillators (SPXOs) are one solution. These continuous voltage oscillators are optimized for low power consumption and low RMS jitter and can operate at any voltage between 1.60 V and 3.60 V, enabling designers to achieve solution.
This article will briefly discuss some of the important performance requirements and design challenges that must be overcome to successfully design timing circuits using discrete quartz crystals and timing ICs. It then introduces Abracon’s SPXO solutions and shows how designers can use these devices to effectively and efficiently meet the timing needs of electronic systems.
Crystal Oscillator Operation and Design Challenges
Power consumption is an important consideration for small battery-operated wireless devices. Many similar devices are based on extremely low-power system-on-chip (SoC) radios and processors that can support years of battery life. In addition, since the battery can be the most expensive component in the system, minimizing the size of the battery is important to control equipment costs. That said, standby current tends to be the most important battery life consideration in small wireless systems, and standby current tends to be dominated by the clock oscillator. Therefore, it is crucial to minimize the current consumption of the oscillator.
Unfortunately, designing low-power oscillators can be a challenge. One way to save energy is to minimize standby current by going into a “disabled” state and starting the oscillator when needed. However, requiring a crystal oscillator to start up quickly and reliably is not an easy task. Designers need to ensure that the oscillator is in a low current state during standby and has reliable start-up characteristics under all operating and environmental conditions.
The configuration of the Pierce oscillator is common in low-power wireless SoCs (Figure 1). Pierce oscillators are built on a crystal (X) and load capacitors (C1 and C2) surrounded by an inverting amplifier using internal feedback resistors. Under the right conditions, when the output of the amplifier is fed back to the input, a negative resistance develops and oscillation occurs.
Figure 1: Basic Pierce oscillator configuration built around a crystal (X) and load capacitors C1 and C2. (Image credit: Abracon)
Crystal structures are complex; this discussion is only about the top-level and simplified structure of crystals operating in oscillators.
The closed-loop gain margin Gm can be used as a figure of merit (FOM) to describe the reliability of the oscillator with respect to various losses. The closed-loop gain margin is also known as oscillation margin (OA). An OA below 5 results in low production throughput and temperature-related startup issues. Designs with an OA value of 20 or higher are robust, operate reliably over the design operating temperature range, and have minimal impact on crystal and SoC performance characteristics between different production batches.
To measure the OA of the oscillator, a variable resistor Ra can be added to the circuit (Figure 2). Increase the Ra value until the oscillator fails to start. This is what is used to determine the OA value, as follows:
Rn is the negative resistance
Re is the equivalent series resistance (ESR).
Among them, the calculation method of load capacitance CL is as follows:
where Cs is the circuit’s variable capacitor, typically between 3.0 and 5.0 pF.
Figure 2: Shows the extended crystal model (middle box) and the adjustable resistor (Ra) used to measure the oscillation margin. (Image credit: Abracon)
OA depends on ESR (Re), and ESR depends on quartz crystal parameter Rm and load capacitance CL. For low-power oscillators, such as those used in low-power wireless devices, the effect of Rm and CL on OA can be increased. Measuring OA is time-consuming and can lengthen the development process. As a result, this work may be overlooked, resulting in performance issues when the system or device is put into production.
Also, ensuring reliable oscillator operation by setting high OA can cause other problems. For example, the higher the OA, the higher the oscillator circuit performance, but the power loss due to the crystal may be ignored. This loss can be an important factor. Looking again at Figure 2, the crystal motion resistor Rm causes power dissipation as current flows through the resistor periodically. When CL is larger, current and losses increase. Therefore, the designer needs to strike a balance between the power loss of the crystal and a reasonable OA value.
Understanding and reducing jitter is important when designing a crystal oscillator. There are two types of jitter, both usually measured in rms:
・ Cycle-to-cycle jitter: Also called phase jitter, it refers to the maximum time difference between several measured oscillation cycles, usually at least 10 cycles are measured.
• Period jitter: This is the maximum variation of a clock edge, measured per cycle, not multiple cycles.
The main sources of jitter in crystal oscillators include power supply noise, integer harmonics of the signal frequency, improper loading and termination conditions, amplifier noise, and certain circuit configurations. Depending on the source, different methods can be used to minimize jitter.
・ Use bypass capacitors, chip beads, or resistive capacitor (RC) filters to control power supply noise.
• In critical applications requiring extremely low jitter, it is critical to establish a method to control harmonics (outside the scope of this article).
・ Reduce the power reflected back to the output by optimizing the load and termination conditions.
• Avoid designs that include phase-locked loops, multipliers, or programmable functions, as they tend to increase jitter.
・ Continuous Voltage Crystal Oscillator
Using Abracon’s ASADV, ASDDV, and ASEDV SPXOs facilitates designing systems with bias voltages ranging from 1.60 to 3.60 V (Figure 3). The SPXO family covers different frequency ranges; 1.25 MHz to 100 MHz for ASADV devices and 1 MHz to 160 MHz for ASDDV and ASEDV devices. The series are RoHS/RoHS II compliant and housed in hermetic ceramic surface mount device (SMD) packages. The frequency stability of this series is ±25ppm over the operating temperature range of -40°C to +85°C.
Figure 3: ASADV (shown), ASDDV, and ASEDV SPXO are available in hermetic ceramic packages and operate over a temperature range of -40°C to +85°C. (Image credit: Abracon)
The dimensions of the ASADV are 2.0 x 1.6 x 0.8 mm, the dimensions of the ASDDV are 2.5 x 2.0 x 0.95 mm, and the dimensions of the ASEDV are 3.2 x 2.5 x 1.2 mm. The three families operate over a wide range of common operating temperatures, offer a variety of stability options, and CMOS/HCMOS/LVCMOS compatible output formats.
Importantly, the ASADV, ASDVD and ASEDV families are optimized for low current operation (Figure 4). The output enable/disable function reduces current to only 10 μA when disabled. The maximum startup time for these devices is 10 ms.
Figure 4: ASEDV’s current consumption versus supply voltage, typical of this SPXO family of devices (measured at 25°C ±3°C). (Image credit: Abracon)
All three families of SPXOs feature exceptionally low current consumption. For ASADV, the maximum current ranges from 1.0 mA at 1.25 MHz and 1.8 V supply to 14.5 mA at 81 MHz and 3.3 V supply when measured at 25°C with a 15 pF load. For ASDDV and ASEDV, the maximum current ranges from 1.0 mA at 1 MHz and 1.8 V supply to 19 mA at 157 MHz and 3.3 V supply.
These devices can drive multiple loads with good electromagnetic interference (EMI) performance and low jitter performance.The rms phase jitter of these devices
Figure 5: These SPXOs have good frequency stability over the entire operating temperature range. The figure is typical of the ASEDV series. (Image credit: Abracon)
Finally, ASADV, ASDVD, and ASEDV continuous voltage surface mount crystal oscillators can be used as low-cost alternatives to microelectromechanical systems (MEMS) oscillators when shock and vibration are not critical considerations.
Designers need accurate and reliable oscillators that provide stable timing over a wide range of applications and operating temperatures. Discrete crystal-controlled oscillators can meet the required performance characteristics, but it is technically difficult to design with crystals effectively, and is time-consuming and unnecessary cost. In addition, it is not optimal in terms of external dimensions.
As shown, designers can use low-power integrated SPXOs. This SPXO forms a ready-to-use timing solution with excellent frequency stability over a wide operating temperature range. Using SPXOs, designers can reduce component count, reduce solution size, reduce assembly costs, and increase reliability.